Technical Field
The present invention relates to semiconductor devices, and more particularly to devices and methods for fabricating such devices with work function setting metal layers, which are more compatible with narrower spaces between semiconductor regions.
Description of the Related Art
In nanometer scale devices, gate structures are often disposed between fin structures or other conducting structures, such as nanosheets. In many instances, the conducting or semiconducting structures are formed closer together due to scaling to smaller node technology sizes. This can be a limiting factor in the reduction of the device size scaling. With narrower gaps, it becomes more important to prevent oxygen diffusion between and into these narrow structures. In one example, a gate structure that permits oxygen diffusion into the gate dielectric can experience detrimental threshold voltage changes.
While finFETs and/or nanosheets can benefit from tight device-device spacing, these dimensions may limit scaling of these devices. Further, devices requiring thicker dielectric for higher voltage operation are even more severely limited in the allowable dimensions.